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Module register

Module register 

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The SX127x register map, its SPI framing, and its operating modes.

An SX1276, SX1277, SX1278, or SX1279 is driven through registers rather than commands. Each access is one SPI transaction framed by NSS: an address byte whose most significant bit is 1 for a write and 0 for a read, then the data bytes. The address advances with each further byte, except at FIFO, where every byte goes to or comes from the LoRa data buffer. The addresses are those of Table 41 of the SX1276/77/78/79 datasheet (Rev 7) with the LoRa register page selected, and Mode holds the Mode bits of RegOpMode.

Enums§

Mode
An operating mode, the Mode bits 2 to 0 of RegOpMode.

Constants§

ACCESS_SHARED_REG
RegOpMode bit 6: the FSK register page while in LoRa mode.
DETECTION_THRESHOLD
RegDetectionThreshold: the LoRa detection threshold.
DETECT_OPTIMIZE
RegDetectOptimize: the automatic IF and the LoRa detection optimization.
DIO_MAPPING_1
RegDioMapping1: the events DIO0 to DIO3 signal.
DIO_MAPPING_2
RegDioMapping2: the events DIO4 and DIO5 signal.
FIFO
RegFifo: the LoRa data buffer, read or written a byte at a time at FIFO_ADDR_PTR.
FIFO_ADDR_PTR
RegFifoAddrPtr: where in the data buffer the next FIFO access lands.
FIFO_RX_BASE_ADDR
RegFifoRxBaseAddr: where in the data buffer received payloads start.
FIFO_RX_CURRENT_ADDR
RegFifoRxCurrentAddr: where the last received packet starts in the data buffer.
FIFO_TX_BASE_ADDR
RegFifoTxBaseAddr: where in the data buffer a transmitted payload starts.
FRF_LSB
RegFrfLsb: the least significant byte of the carrier frequency word.
FRF_MID
RegFrfMid: the middle byte of the carrier frequency word.
FRF_MSB
RegFrfMsb: the most significant byte of the carrier frequency word.
HIGH_BW_OPTIMIZE_1
RegHighBwOptimize1, which the 500 kHz sensitivity erratum sets.
HIGH_BW_OPTIMIZE_2
RegHighBwOptimize2, which the 500 kHz sensitivity erratum sets.
HOP_CHANNEL
RegHopChannel: the PLL lock and the CRC the last header announced.
IF_FREQ_1
RegIfFreq1, which the spurious reception erratum clears.
IF_FREQ_2
RegIfFreq2, which the spurious reception erratum sets per bandwidth.
IMAGE_CAL
RegImageCal, at the same address as INVERT_IQ_2 on the FSK register page.
INVERT_IQ
RegInvertIQ: the IQ polarity of the receive and transmit paths.
INVERT_IQ_2
RegInvertIQ2, which completes an IQ inversion.
IRQ_FLAGS
RegIrqFlags: the interrupts raised, each cleared by writing it back as a 1.
IRQ_FLAGS_MASK
RegIrqFlagsMask: the interrupts masked off.
LNA
RegLna: the LNA gain and current.
LONG_RANGE_MODE
RegOpMode bit 7: the LoRa modem rather than FSK, changed only in Mode::Sleep.
LOW_FREQUENCY_MODE_ON
RegOpMode bit 3: the low frequency test registers, set at reset.
MAX_PAYLOAD_LENGTH
RegMaxPayloadLength: the longest payload a received header may announce.
MODEM_CONFIG_1
RegModemConfig1: bandwidth, coding rate, and header mode.
MODEM_CONFIG_2
RegModemConfig2: spreading factor, CRC, and the top bits of the symbol timeout.
MODEM_CONFIG_3
RegModemConfig3: low data rate optimization and the automatic gain control.
MODEM_STAT
RegModemStat: the live state of the LoRa modem.
OCP
RegOcp: the over current protection of the amplifier.
OP_MODE
RegOpMode: LoRa or FSK, the register page, and the operating mode.
PAYLOAD_LENGTH
RegPayloadLength: the payload length to transmit, or to expect in implicit header mode.
PA_CONFIG
RegPaConfig: the amplifier output pin, its maximum power, and the output power.
PA_DAC
RegPaDac: the +20 dBm setting of the PA_BOOST amplifier.
PA_RAMP
RegPaRamp: the amplifier ramp time.
PKT_RSSI_VALUE
RegPktRssiValue: the RSSI of the last packet.
PKT_SNR_VALUE
RegPktSnrValue: the SNR of the last packet, in quarters of a decibel.
PREAMBLE_LSB
RegPreambleLsb: the low byte of the preamble length.
PREAMBLE_MSB
RegPreambleMsb: the high byte of the preamble length.
RSSI_VALUE
RegRssiValue: the RSSI the receiver hears right now.
RSSI_WIDEBAND
RegRssiWideband: a wideband RSSI sample, noisy enough to seed a random number.
RX_NB_BYTES
RegRxNbBytes: the payload length of the last packet received.
SYMB_TIMEOUT_LSB
RegSymbTimeoutLsb: the low byte of the single reception timeout, in symbols.
SYNC_WORD
RegSyncWord: the LoRa sync word.
TCXO
RegTcxo: a crystal or a TCXO on the XTA pin.
VERSION
RegVersion: the silicon revision.
VERSION_SX1276
The RegVersion value of an SX1276, SX1277, SX1278, or SX1279, and of the modules built on them.
WRITE
The bit of the address byte that makes an access a write.

Functions§

fsk_op_mode
Returns the RegOpMode value for an FSK operating mode, which image calibration needs.
lora_op_mode
Returns the RegOpMode value for a LoRa operating mode.
read_address
Returns the address byte that reads a register.
write_address
Returns the address byte that writes a register.