Struct MaskEnable 

pub struct MaskEnable {
    pub shunt_over_limit: bool,
    pub shunt_under_limit: bool,
    pub bus_over_limit: bool,
    pub bus_under_limit: bool,
    pub power_over_limit: bool,
    pub conversion_ready: bool,
    pub alert_function_flag: bool,
    pub conversion_ready_flag: bool,
    pub math_overflow: bool,
    pub alert_active_high: bool,
    pub alert_latch: bool,
}

The Mask/Enable register (0x06): which alert function drives the pin, how the pin behaves, and the status flags the chip reports back.

The alert limit register is compared in the units of the selected function, so build it with shunt_register, bus_register, or power_register.

Fields

shunt_over_limit: bool

Assert the alert pin when the shunt voltage exceeds the limit (SOL).

shunt_under_limit: bool

Assert the alert pin when the shunt voltage drops below the limit (SUL).

bus_over_limit: bool

Assert the alert pin when the bus voltage exceeds the limit (BOL).

bus_under_limit: bool

Assert the alert pin when the bus voltage drops below the limit (BUL).

power_over_limit: bool

Assert the alert pin when the power exceeds the limit (POL).

conversion_ready: bool

Also assert the alert pin when a conversion completes (CNVR).

alert_function_flag: bool

Status: the selected alert function, not conversion-ready, caused the last alert (AFF).

conversion_ready_flag: bool

Status: all conversions, averaging, and multiplications are complete (CVRF).

math_overflow: bool

Status: an arithmetic overflow occurred and current and power may be invalid (OVF).

alert_active_high: bool

Alert pin polarity: true for inverted (active-high), false for the default active-low (APOL).

alert_latch: bool

Latch the alert pin and flag until this register is read, rather than clearing when the fault clears (LEN).

Implementations

impl MaskEnable

pub fn from_register(raw: u16) -> Self

Decodes a Mask/Enable register value.

Arguments

• raw - the 16-bit Mask/Enable register.

Returns

The decoded enables and flags; reserved bits are ignored.

pub fn to_register(self) -> u16

Encodes the enables and flags as a Mask/Enable register value.

Returns

The 16-bit register to write.

pub fn active_alert_function(self) -> Option<AlertFunction>

Returns the alert function the pin actually responds to.

Only one limit function can drive the pin at a time; when several are enabled the chip honours the most significant bit.

Returns

The highest-priority enabled function, or None if no limit function is enabled.

Trait Implementations

impl Clone for MaskEnable

fn clone(&self) -> MaskEnable

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for MaskEnable

impl Debug for MaskEnable

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for MaskEnable

fn default() -> MaskEnable

Returns the “default value” for a type.

impl Eq for MaskEnable

impl PartialEq for MaskEnable

fn eq(&self, other: &MaskEnable) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl StructuralPartialEq for MaskEnable